Digital indicator with pulse multiplier for providing continous full scale resolution

ABSTRACT

An analog-to-digital converter of a dual-slope integrating voltage-to-proportional-count device cooperates with a pulse multiplier to control full-scale resolution of measurements for different transducer inputs, the fixed-rate pulse output of the converter alternately being coupled to a binary-coded decimal counter for a preselected count interval during first predetermined integrating periods while an unknown transducer input is sampled, and being in synchronized control of the supply of pulses to the same counter at selected multiplied rates during second periods while a reference potential is referred to; a visual readout operated by the counter indicates the measurements with a resolution improved by the pulse-multiplication.

United States Patent Senour et al.

[ 1 Apr. 17, 1973 [54] DIGITAL INDICATOR WITH PULSE MULTIPLIER FORPROVIDING CONTINOUS FULL SCALE RESOLUTION [75] Inventors: Donald A.Senour, Carlislef Tariusi S. Kobel, Cambridge, both of Mass.

OTHER PUBLICATIONS Electronic Design; Vol. 6; No. 2; Jan. 22, 1958;pages 44-45.

Primary ExaminerRudolph V. Rolinec Assistant Examiner-Ernest F. KarlsenAttorney-Thomson & Mrose [57] ABSTRACT An analog-to-digital converter ofa dual-slope integrating voltage-to-proportional-count device cooperateswith a pulse multiplier to control full-scale resolution of measurementsfor different transducer inputs, the fixed-rate pulse output of theconverter alternately [52] "324/99 324/115 340/347 AD being coupled to abinary-coded decimal counter for a [51] f 17/06 Golf 15/08 13/20preselected count interval during first predetermined [58] F mid ofSearch ..324/99 D, 99 R, l 15, integrating periods while an unknowntransducer input 324/100; 340/3 7 AD is sampled, and being insynchronized control of the supply of pulses to the same counter atselected mul- [56] References Cited tiplied rates during second periodswhile a reference potential is referred to; a visual readout operated byUNITED STATES PATENTS the counter indicates the measurements with aresolution improved by the pulse-multi lication. 3,617,885 ll/l97lWheable ..324/ll5 p FOREIGN PATENTS OR APPLICATIONS 6 Chin" 2 DrawingFilm 1,564,758 3/1969 France ..324/99 D i v "l i T' I wAbflskgpE do co RINTEG on NT L TRANSDUCER COEPARATO LOGIC I Cl CUITRY l- I 050. F -----l-I rw I I 24 V, I 500 l20kHz c-I COUNTH? CLOCK J L 32 L. 2i 1 m l 40, i imm/ I 1.2 MHz I nd STORAGE CLOCK l I i.. v 22} Y I CODE/7 46 5 mm? 48LLaw, 39. .EJ I i o. .m .M l 'HEADOl/T Q80 72 l PATENTED $728,625

SHEET 2 OF 2 GATE -92 BCD COUNTER 1 CLOCK INVERTER #95 *i L/m .J

7 (0| PROGRAMMABLE I FLIP- o .fl DIVIDER 4 99 I i 42 I GATE -40 L2 M HzCLOCK INVENTORSZ JANUSZ S.KOBEL BY DONALD A. SENOUR jflomdm 'w z ATTORNEYS DIGITAL INDICATOR WITII PULSE MULTIILIER FOR PROVIDING CONTINOUSFULL SCALE RESOLUTION BACKGROUND OF THE INVENTION The present inventionrelates to improvements in measurement resolution of digital indicatinginstruments, and, in one particular aspect, to unique high-accuracydigital indicating voltmeters in which synchronized clock-pulsemultiplication enchances full-scale resolution capabilities formeasurements of voltage outputs from transducers having dissimilarranges of operation, such as a variety of strain-gage transducersdesigned to respond to different maximum loads.

Digital indicating instruments based upon computertype circuitry anddigital character displays have become highly practical devices whichare both exceedingly rapid in operation and are easily read. Theresolutions of measurements by such devices are of course limited by thenumber of display digits involved, and by the relationships betweenchanges in the least significant digit and accurately-sensed changes inwhatever is being measured. In the case of a five-digit display by adual-slope integrating digital voltmeter, for example, there may be ause in which the voltmeter responds to the output from a 10,000-poundload cell transducer, and the voltmeter system accuracy may be such thatthe display may register the full 10,000 lbs. with a l-pound resolution,or a resolution of 0.01 percent of full scale. The said dual-slopeintegrating voltmeter includes circuitry which translates the measuredvoltage into a related count of pulses, and, in thestated example, theprecision is such that each pulse of 10,000 pulses would characterizeone pound of the measured load. If the same digital voltmeter is nextcalled upon to respond to a 2,000-pound output from the same loadcelltransducer, or from one which also produces voltage outputs on the samelinear scale as the aforesaid 10,000 pound cell, both the pulse countand related digital readout would be 2,000, with the same l-poundresolution; however, the full-scale resolution in such a case would bel-out-of 2,000, or a much coarser 0.05 percent of full scale resolution(vs. the said 0.01 percent). The resolution in the latter case could beimproved by resorting to use of a digital voltmeter having a largernumber of digits and a capability of producing more pulses per incrementof measured voltage, but this would add significant cost and complexity.In accordance with teachings of the present invention, however, a singleintegrating digital indicating instrumentation system overcomes theaforementioned type of resolution problem, without addition of a furtherdisplay digit and its related supporting hardware and electronicnetworks, by way of one programmable synchronized pulse-multiplier unitassociated with the voltage-to-count circuitry of the system. Themultiplier unit, when operated in the cited case of measurementsinvolving a 2,000 pound cell output, would then produce 20,000measurement-related pulses, rather than 10,000, and the five-digitdisplay would then read 2,000.0 pounds, with a resolution of 0.2 pound,such that there would be a desired percent resolution for the2,000-pound reading.

SUMMARY OF THE INVENTION The present invention is aimed at creating animproved and highly precise digital measurement system which isparticularly suitable for displays, with optimum full-scale resolution,of the load measurements by a variety of different range load celltransducers or the like. In a preferred embodiment, the single or summedD. C. analog output voltage from strain-gage load-transducer bridgecircuitry is applied as input to an analog-to-digital converter of aknown type in which, periodically, the input is first integrated for apredetermined interval determined by generation of a fixed number ofpulses by a clock oscillator, the integrated signal then beingdischarged down to a reference potential in a second interval as timedby further clock pulses whose number characterizes the measured voltage.Improvement of full-scale resolution is brought about by pre-selectedpulse multiplications during the second intervals, these multiplicationsbeing synchronized with the clock oscillator and involving theproduction of a selected integral multiple number of pulses for eachoccurrence of a clock pulse. Counting and digital display of the numbersof pulses occuring during the aforesaid second intervals is performed byconventional readout equipment which indicates the measured load, therebeing a direct correlation between the numbers of pulses and the poundsof load measured by the transducer circuitry.

Accordingly, it is one of the objects of the present invention toprovide a unique high-precision digital indicating system which affordsimproved full-scale resolutions of a variety of measurement inputs.

Another object is to provide an integrating-type digital voltmeter inwhich synchronized pulse-multiplications enhance resolutions of certainmeasurements without necessitating incorporation of additional digits inassociated readout equipment.

A further object of the invention is the provision of apulse-multiplying digital indicator in which the numbers of pulses whichcontrol the digital readout of measurement data are integrallymultiplied to cause resolutions of readouts for different levels ofinput signals to be improved.

Still further, it is an object to provide an integratingtype digitalvoltmeter wherein clocking pulses synchronize and control the productionof programmable integral multiples of voltage-to-count pulses, therebyenabling full-scale resolutions to be adjusted without attendantlikelihood of measurement error.

BRIEF DESCRIPTION OF THE DRAWINGS Further details concerning preferredpractice of the invention, as well as additional features, objects andadvantages thereof, may best be perceived in connection with thefollowing description taken in connection with the accompanyingdrawings, wherein:

FIG. 1 is a block schematic diagram of an improvedresolution digitalvoltmeter system; and

FIG. 2 is a partly schematic and partly block-diagrammed circuitillustrating certain details of the system ofFIG. l.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1, asolid-state digital indication system expressing the present inventionis intended to respond to DC. input signals developed by a measurementdevice 9, such as a strain-gage load-cell transducer or array oftransducers. Typically, the strain gages in well-known forms oftransducers are connected in bridge configuration, and the bridge outputvoltages bear a substantially direct relation to impressed loading.Translation of these output voltages into digital characterizations ofthe load under measurement may be accomplished by way of a dual-slopeintegrating voltmeter arrangement, 11, involving dual-slope integratorcomparator circuitry 10, control logic circuitry 14, and an associatedpulse generator or clock, 18, the latter being illustrated as a 120 KHzclock. A conventional output from a known type of network 11 wouldinclude periodic bursts of pulses, the number of pulses in each burstbeing directly related to the input terminal 12, with the output pulsesin turn being delivered to a binary-codeddecimal (BCD) counter 20. Eachcounted burst of such pulses is stored in a conventionalintegrated-circuit latch storage unit 44, and the output of the latterexcites a conventional decoder driver 46 driving the stages of a visualreadout device 48. The decimal digital equivalent of the informationappearing in counter 20 is thus reproduced on the readout device, whichmay comprise an appropriate number of digital display tubes, such asNixie tubes in seven-segment arrays, or the like. By way of example, thereadout device 48 may comprise known units manufactured for that purposeby Burroughs Corporation or National Electronics Company, and the items20, 44 and 46 may comprise Texas Instruments Company Series 7400 TTL(transistor-transistor logic) units such as a BCD Counter Part No. 7490N, a Latch Storage Device, Part No. SN 7475 N, and a decoder Driver PartNo. SN. 7441 N, respectively. Analog-to-digital conversion in item 11may be achieved with the Series 2300, Part No. 2317, apparatusmanufactured for that purpose by Analogic Company, Wakefield,Massachusetts.

In relation to better appreciation of the specific improvements realizedthrough practice of the present invention, it is helpful to considerfirst certain of the operating characteristics of a conventional form ofdual-slope integrating voltmeter network 11. C01- laterally, referencemay be had to the descriptions contained in US. Pat. No. 3,368,149,issued Feb. 6, 1968, for example. As has already been alluded to, anobjective of network 11 is to produce successive bursts of pulses, thenumber of pulses in each burst being directly related to the inputvoltage witnessed at terminal 12. Implementation of that objectiveinvolves the use of an oscillator 13, such as a conventional form ofunijunction oscillator, which will deliver output pulses to units 11 and20 at a given repition rate to initiate successive readings ordevelopment of the aforesaid successive bursts of pulses, and to resetor clear the counter 20. On command of each such output pulse fromoscillator 13, the integrator/comparator circuitry commences integrationof the input signal at terminal 12, and, simultaneously, clock 18 iscontrolled by logic 14 to commence a precise timing operation in whichit delivers pulses at a precise rate to counter 20. In the illustration(FIG. 1), the pulses from clock 18 are passed to counter 20 throughgating circuit 19 and couplings 19a and 19b. Once a predetermined pulsecount has been reached in counter 20, on the occurrence of the 10,000thpulse for the five stages 30, 32, 34, 36 and 38 of counter 20, aresulting pulse is supplied to control logic circuitry 14 via coupling24, causing the latter to reset the counter to a cleared condition andto initiate a discharge of a previously-integrated signal inintegrator/comparator 10 back down to a predetermined low referencelevel, such as a system ground or zero level. Clock 18 feeds its pulseoutput to counter 20 during this second or discharge step until logiccircuitry commands it to stop, which occurs when the aforesaid zerolevel is reached. Slope of the decreasing voltage is constant, and thetime to reach the zero level is thus accurately proportional to thepreviously-integrated voltage, the latter in turn being preciselyrelated to the voltage at terminal 1.2 because the time of itsintegration was closely governed by clock 18. In the remaining intervalbefore the next succeeding output pulse is developed by oscillator 13,the count developed in the binary coded decimal counter 20 during theaforementioned second step of measurement operation is stored in theintegrated-circuit latch storage unit 44, which includes five stages,50, 52, 54, 56, and 58, one corresponding to each stage of the counter20. In turn, the latch storage output is decoded to a decimalrepresentation thereof in a conventional decoder driver 46, whichsimilarly includes five stages, 60, 62, 64, 66 and 68, corresponding tothe stages of unit 44. Decoder 46 incorporates the appropriate driversfor driving the respective five stages 70, 72, 74, 76 and 78 of visualreadout 48, the latter indicating visually the decimal equivalent of thebinary coded information appearing in counter 20. A known form ofpolarity-indicating readout stage 80 may also be provided. Therepetition rate for the cyclic system readings is high enough for thereadout to track expected changes in input signals, such as threereadings per second.

If the transducer 9 is one which develops a predetermined maximum outputvoltage, such as 5.000 volts, characterizing a full load of 10,000pounds, for example, the'five-digit display of readout 48 will have afullrange resolution of one pound out of the 10,000, or 0.01 percent.This corresponds to the accuracy of one counted pulse out of a total ofthe 10,000 pulses counted during the second or discharge step in eachcycle of operation of the integrator/comparator 10. For a givenrepetition rate of counting pulses from the master clock 18, theintrinsic measurement accuracy of the system is fixed; however, thesecond-step or output pulses which are counted for related display bythe readout 48 are nevertheless advantageously multiplied in accordancewith this invention to permit the same input voltage to be translatedinto an integrally-multiplied readout value or to permit a smaller inputsignal to be displayed as a readout with the same full-scale resolutionas a larger signal. By way of illustration, a 5.000 volt input signalwhich is produced by the aforesaid 10,000-pound transducer may also beproduced by 20,000-pound, 30,000-pound, 40,000- pound, etc. transducers(either directly or because of signal conditioning by the associatedpreamplifiers used in the transducers), and proper readouts from thelatter should involve a multiplication by two, three, four, etc. Or,where readings such as up to a 1,000- pound reading are to be obtainedfor outputs up to 0.5 volt from the aforesaid 10,000-pound transducer, amultiplication by ten would give a full five-digit reading of up to the1,000.0 pounds with an accuracy of up to 0.1 pound, or, again, theaforesaid 0.01 percent for the newly-selected full range of 1,000pounds. These results are obtained by developing appropriate integralmultiples of each of the pulses from master clock 18 only during thosecount-down intervals when the previously-integrated input signals arebeing discharged to the reference or zero level in integrator/comparatorl0. Importantly, these integral multiplications are synchronized withand occur well within the periods between successive pulses from clock18, otherwise readout errors could be caused.

For the aforementioned multiplication purposes, a pulse multiplierarrangement 22 is in a slaved synchronized relation to the master clock18 and is programmed or set to insure that the desired pulse multiplesare produced and fed to BCD counter 20. The multiplier includes a secondclock or pulse oscillator, 40, which is selected to generate pulses at afixed repetition rate many times greater than that of master clock 18,such as a 1.2 MHz rate vs. the 120 KHz rate of clock 18. A programmabledivider 42 divides the pulses from auxiliary clock 40 by any of apredetermined integral number of divisions for which it is designed,such as from two to ten, and may be known Modulo-n type device such asthat which is made by National Semiconductor Company under Part No. DM8520.

As each pulse is developed by master clock 18 at the 120 KHZ rate duringeach second or count-down interval of operation of integrator/comparator10, it is applied in control of the auxiliary pulse-multiplyingoscillator 40, and the latter responds to this command by producing atrain or burst of pulses at the 1.2 MHz rate. Programmable divider 42,which has been set to divide the pulse output of auxiliary oscillator40, is responsible for the predetermined set number of pulses beingpassed to the BCD counter via the gating circuitry 19. Depending uponthe selected setting of divider 42, counter 20 will witness 2, 3, 4, 5etc. short rapid pulses for each occurrence of a master clock pulseduring the count-down interval. It is important that the operation ofthe auxiliary clock 40 be slaved in relation to that of the masterclock, and that the repetition rate of clock 40 be much greater(example: ten times) than that of clock 18, to avoid the likelihood ofcounting errors.

In FIG. 2, which includes further details of certain features of theimproved system shown in FIG. 1, the aforementioned BCD counter 20receives its pulses from a known form of gating circuitry l9 whichinvolves a pair of And gates 81 and 82 delivering their outputs tocoupling 19b through an Or gate 83. When the integration of an inputsignal at terminal 12 (FIG. 1) is about to commence, a recycling pulsefrom unijunction oscillator 13 is applied to terminal 84 (FIG. 2) of aknown form of set-reset flip-flop circuit or quadrature Nand gate 85,including Nand gates such as 86-89. The Nand units respond to therecycling pulse by producing a gating signal in coupling 90, the latterappearing at the input of And unit 81 and enabling the same to pass 120KHZ master-clock pulses which appear there via coupling 91. The lattermaster clock pulses are of course developed by clock 18, as enabled by aknown form of associated gate 92 whose logic inputs 93 and 94periodically turn the clock on upon appearance of a recycling pulse fromoscillator 13 and then turn it off when the integrator/comparator 10produces a crossover output signalling that the previously-integratedinput voltage has been discharges to the ground or reference level.Inverter 95 merely serves to develop a desired polarity of the clockpulse outputs. When the integration of the input voltage is completed,an occurrence of the 10,000th clock pulse in the specific case underconsideration, a control signal is applied to terminal 96 of circuit 85,and circuit thereupon terminates the enabling gate signal theretoforeimpressed at the input of And unit 81, preventing further passage ofmaster-clock pulses to counter 20. Simultaneously, the Nand-unit circuit85 delivers an enabling gate signal to the input of And unit 82 of gate20, via coupling 97. At that juncture, the gate 19 is readied to pass tothe counter 20 only the multiplied pulses which are to improve theresolution of measurement in accordance with the principles explainedearlier herein.

The aforesaid multiplied pulses are developed in coupling 98, as theresult of interactions between clock 18, auxiliary clock 40,programmable'divider 42, and a flip-flop circuit 99. For this purpose,the inverted output pulses from 120 KHZ clock 18 are differentiated by adifferentiator to produce turn-on spike pulses for application to theType D flip-flop 99, which is one which is turned on and off by appliedpulses. The output of flip-flop 99, in response to each differentiatedor spike input pulse, is applied to a gate portion 40a of a known formof auxiliary clock 40, which is designed to generate successive pulsesat a 1.2 MHz rate many times (ten) the rate at which pulses are producedby master clock 18. When high-repetition rate clock 40 is thus gatedinto synchronized operation by the master clock, it delivers its pulsesto both the programmable divider 42 and the aforesaid input to gate 19,over coupling 98. Depending upon its setting, divider 42 will allow onlya predetermined integral number of auxiliary-clock pulses, such as 2, or3, or 4, etc., to be produced each time the clock 40 is gated intooperation. Divider 42 is of a known form which will determine when apredetermined number of pulses appear on line 98 and will then apply arelated inhibiting signal to flip-flop 99 over line 101, whereby theauxiliary clock 40 ceases to deliver output pulses until the next gatingoccurs in response to a master-clock pulse. In one convenient version, aModulo-n divider has its dividing program set byway ofmanually-connected jumpers 102 applying appropriate logic 1 and 0signals from a source 103 to the divider terminals 104 in apredetermined BCD code, All clock pulses cease when gate 92 disablesmaster clock 18 upon occurrence of a crossover signal at the end ofcount-down of the integrated input voltage. The described cycle ofoperation is repeated upon recurrence of a recycling pulse signal fromoscillator 13, such that the readout count may change along with changesin the system input signal.

it should be understood that the specific preferred embodiment andpractices described herein have been presented by way of disclosurerather than limitation, and that those skilled in the art willappreciate that various modifications, combinations and substitutionsmay be effected without departure from the spirit and scope of thisinvention in its broader aspects and as set forth in the accompanyingclaims.

What we claim as new and desire to secure by Letters Patent of theUnited States is:

1. An electronic digital indicator system comprisingintegrator/comparator means cyclically integrating applied electricalinput signal during first predetermined periods of time and determiningthe magnitudes of said input signal in terms of second periods of timewhich it takes for the integrated signal to assume a predeterminedrelation to a reference condition, timing means for producing periodicbursts of pulses at a predetermined repetition rate, said timing meanscomprising a master clock oscillator producing pulses at saidpredetermined rate, and an auxiliary clock oscillator responsive to saidmaster oscillator pulses producing pulses at a repetition ratesufficiently higher than said predetermined rate for a relatively largenumber of pulses to be produced by said auxiliary oscillator for eachpulse produced by said master oscillator, means synchronizing thecommencement of the first and last burst of pulses of each of saidperiodic bursts of pulses with the beginning and end, respectively, ofeach of said second periods of time, means for selectably varying thenumber of pulses produced in each of said bursts of pulses by saidtiming means, said means for selectably varying said number of pulsescomprising a programmable divider controlling the number of pulsesproduced by said auxiliary oscillator at said higher rate in response toeach pulse produced by said master oscillator, and means providing adigital display characterizing the total number of pulses produced bysaid timing means during each of said second periods of time, theselective variations in the number of pulses produced in each of saidbursts of pulses providing for adjustment or measurement resolution bysaid display means.

2. An electronic digital indicator system as set forth in claim 1wherein said master clock oscillator controls said first periods of timein said integrator/comparator means, and wherein said programmabledivider controls said auxiliary oscillator to produce an integral numberof pulses at said higher rate within the periods of time betweencommencements of successive pulses from said master clock oscillator.

3. An electronic digital indicator system as set forth in claim 1wherein said input signal is a voltage, wherein determining themagnitude of said input signal involves measuring the times for 'theintegrated input voltage to discharge to a lower predetermined referencelevel, wherein said means providing a visual display includes a counter,and wherein said timing includes gating means coupling pulses developedby said master clock oscillator to said counter, means controlling theduration of said first periods of time in said integrator/comparatormeans in accordance with counts by said counter of a predeterminednumber of pulses developed by said master clock oscillator, and

means controllin said gatjn means to con le to said counter the selecbly-varie number of pu ses in said bursts of pulses.

4. An electronic digital indicator system as set forth in claim 3wherein said auxiliary clock oscillator comprises a gated oscillator,means applying said pulses produced by said master oscillator duringsaid second periods to gate said auxiliary oscillator on, and meansapplying signals from said divider to gate said auxiliary oscillator offwhen the selected number of pulses is produced by said auxiliaryoscillator responsive to each pulse from said master oscillator.

5. An electronic digital indicator system as set forth in claim 4wherein said gating means includes a first And gate for coupling to saidcounter pulses developed by said master oscillator during said firstperiods, means cyclically applying an enabling signal to said first Andgate to enable said coupling during said first periods, a second Andgate for coupling to said counter the selectably-varied numbers ofpulses in said bursts of pulses, and means cyclically enabling saidlatter coupling during said second periods each commencing with the endsof said first periods and ending with the last of pulses from saidmaster oscillator during said second periods.

6. An electronic digital indicator system with adjustable full-scaleresolution comprising a digital pulse clock for generating pulses at apredetermined rate, means for cyclically integrating an unknown inputvoltage during first predetermined periods of time as controlled bygenerations of a predetermined number of pulses by said clock, and meansfor cyclically measuring the second periods of time for the integratedvoltage to assume a predetermined relation to a reference potential,said last-named means including a counter, means sensing occurrences ofsaid predetermined relationship, pulse-multiplication means forproducing a selected number of pulses which is an integral multiple ofeach of pulses generated by said clock, gate means passing to saidcounter the pulses from said pulse-multiplication means during saidsecond periods of time as determined by the ends of said first periodsand the sensing of said occurrences by said sensing means, and meansdisplaying readouts related to the counts of multiplied pulses in saidcounter, said pulse-multiplication means including a pulse generatorproducing pulses at a significantly higher repetition rate than saidpredetermined rate in response to each of the pulses generated by saidclock during said second periods, said higher repetition rateoccasioning production by said pulse generator of all of a desiredselectable number of pulses within the span of each of said clockpulses, and said pulse-multiplication means including a modulo-n dividerprogrammable to apply to said gate means a selected number of the totalnumber of pulses produced by said generator in response to each clockpulse during said second periods.

a: i a: m s a

1. An electronic digital indicator system comprising integrator/comparator means cyclically integrating applied electrical input signal during first predetermined periods of time and determining the magnitudes of said input signal in terms of second periods of time which it takes for the integrated signal to assume a predetermined relation to a reference condition, timing means for producing periodic bursts of pulses at a predetermined repetition rate, said timing means comprising a master clock oscillator producing pulses at said predetermined rate, and an auxiliary clock oscillator responsive to said master oscillator pulses producing pulses at a repetition rate sufficiently higher than said predetermined rate for a relatively large number of pulses to be produced by said auxiliary oscillator for each pulse produced by said master oscillator, means synchronizing the commencement of the first and last burst of pulses of each of said periodic bursts of pulses with the beginning and end, respectively, of each of said second periods of time, means for selectably varying the number of pulses produced in each of said bursts of pulses by said timing means, said means for selectably varying said number of pulses comprising a programmable divider controlling the number of pulses produced by said auxiliary oscillator at said higher rate in response to each pulse produced by said master oscillator, and means providing a digital display characterizing the total number of pulses produced by said timing means during each of said second periods of time, the selective variations in the number of pulses produced in each of said bursts of pulses providing for adjustment or measurement resolution by said display means.
 2. An electronic digital indicator system As set forth in claim 1 wherein said master clock oscillator controls said first periods of time in said integrator/comparator means, and wherein said programmable divider controls said auxiliary oscillator to produce an integral number of pulses at said higher rate within the periods of time between commencements of successive pulses from said master clock oscillator.
 3. An electronic digital indicator system as set forth in claim 1 wherein said input signal is a voltage, wherein determining the magnitude of said input signal involves measuring the times for the integrated input voltage to discharge to a lower predetermined reference level, wherein said means providing a visual display includes a counter, and wherein said timing includes gating means coupling pulses developed by said master clock oscillator to said counter, means controlling the duration of said first periods of time in said integrator/comparator means in accordance with counts by said counter of a predetermined number of pulses developed by said master clock oscillator, and means controlling said gating means to couple to said counter the selectably-varied number of pulses in said bursts of pulses.
 4. An electronic digital indicator system as set forth in claim 3 wherein said auxiliary clock oscillator comprises a gated oscillator, means applying said pulses produced by said master oscillator during said second periods to gate said auxiliary oscillator on, and means applying signals from said divider to gate said auxiliary oscillator off when the selected number of pulses is produced by said auxiliary oscillator responsive to each pulse from said master oscillator.
 5. An electronic digital indicator system as set forth in claim 4 wherein said gating means includes a first And gate for coupling to said counter pulses developed by said master oscillator during said first periods, means cyclically applying an enabling signal to said first And gate to enable said coupling during said first periods, a second And gate for coupling to said counter the selectably-varied numbers of pulses in said bursts of pulses, and means cyclically enabling said latter coupling during said second periods each commencing with the ends of said first periods and ending with the last of pulses from said master oscillator during said second periods.
 6. An electronic digital indicator system with adjustable full-scale resolution comprising a digital pulse clock for generating pulses at a predetermined rate, means for cyclically integrating an unknown input voltage during first predetermined periods of time as controlled by generations of a predetermined number of pulses by said clock, and means for cyclically measuring the second periods of time for the integrated voltage to assume a predetermined relation to a reference potential, said last-named means including a counter, means sensing occurrences of said predetermined relationship, pulse-multiplication means for producing a selected number of pulses which is an integral multiple of each of pulses generated by said clock, gate means passing to said counter the pulses from said pulse-multiplication means during said second periods of time as determined by the ends of said first periods and the sensing of said occurrences by said sensing means, and means displaying readouts related to the counts of multiplied pulses in said counter, said pulse-multiplication means including a pulse generator producing pulses at a significantly higher repetition rate than said predetermined rate in response to each of the pulses generated by said clock during said second periods, said higher repetition rate occasioning production by said pulse generator of all of a desired selectable number of pulses within the span of each of said clock pulses, and said pulse-multiplication means including a modulo-n divider programmable to apply to said gate means a selected number of the total number of pulses produced by said generator in response to each clock pulse during said second periods. 